[CONTRACT] UVM Verification Engineer

Job Description

Job: UVM Verification Engineer
Location: Sweden/Remote
Duration: 12 months
Start Date: ASAP

We are currently looking for 3 ASIC verifiers to help our customer in the telecom sector. You will be involved in new and existing ASIC projects working in teams. The team is currently working on a algorithm IP and architecture of the next-generation devices.

We are looking for 3 engineers from same region in Europe to be able to have a tight collaboration

Knowledge and experience:

• 5 years or more experience from ASIC verification 
• Good knowledge of UVM verification and SystemVerilog
• Used to work with complex ASIC and/or large FPGA design
• Experience from IP block verification
• Multi clock domains
• An analytical approach and be results oriented with the ability to deliver under pressure 
• High self-motivation, an ability to work independently while being a great teammate
• Experiences in Formal verification 
• Knowledge of C, Emulation & HLS is preferable

Additional information
Remote work within Europe is is ok, but approximately 2 travels to Sweden each year might be required